1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method.
2. Description of the Related Art
In a semiconductor device such as an LSI, in addition to an MOS transistor, a capacitor is formed on a semiconductor substrate for the purpose of computation processing, storage of information, or the like. Such capacitors may take various types of structures. Among those, a structure in which a lower electrode is formed of the impurity diffusion region of a semiconductor substrate is advantageous in that both the manufacturing process for the capacitor and that for an MOS transistor can be readily carried out in a compatible manner, because a capacitor dielectric film can be formed of the same thermal oxidation film as that forming a gate insulating film of the MOS transistor and an upper electrode can be formed of the same conductive film as that forming a gate electrode.
As described in the following Patent Literature 1, the problem with this type of capacitor is that when the impurity concentration in the impurity diffusion region serving as the lower electrode is low, the surface of a silicon substrate becomes depleted when the voltage applied to the capacitor is low, and hence the capacitance of the capacitor fluctuates. In order to reduce such dependency of the capacitance of the capacitor on the applied voltage, in this type of capacitor, it is preferable to set the impurity concentration in the above-mentioned impurity diffusion region to be as high as possible.
An impurity concentration is determined by the product (dose amount) of a beam current and implantation time of an ion implantation device. Accordingly, conventionally, a high-current ion implantation device capable of generating a high beam current on the order of 10 mA to 20 mA has been used to form the above-mentioned impurity diffusion region, whereby the impurity concentration in the impurity diffusion region has been increased.
However, when the amount of ion implantation to the impurity diffusion region is increased in this way in order to increase the impurity concentration, an amorphous layer is formed on the surface layer of the semiconductor substrate due to the ion implantation, which causes a decrease in the breakdown voltage of the thermal oxidation film that serves as the capacitor dielectric film. This causes another problem that the breakdown voltage between electrodes of the capacitor decreases, and that the decrease results in reduced reliability.
It should be noted that the technique relating to the present invention is also disclosed in the Patent Literature 2.
[Patent Literature 1] Japanese Patent Laid-open No. Hei. 11-330373
[Patent Literature 2] Japanese Patent Laid-open No. Hei. 6-45541